Power (high voltage) field effect transistors are well known. One such transistor is called a DMOS (double diffused metal oxide semiconductor) transistor; for instance see published international application PCT/US96/04175, "Lateral Field Effect Transistor Having Reduced Drain to Source on-Resistance", Hshieh, et al., applicant Silicon Incorporated, incorporated herein by reference in its entirety.
Such transistors (also referred to as MOSFETs) are typically formed on a die which is a portion of a silicon substrate. The actual fabrication involves multiple steps of depositing and etching various materials. The etching steps typically (not always) etch features in one of the layers of material as defined by a masking layer which is a layer of material impervious to the etching material and which defines underlying features as a result of photolithography to pattern the masking layer. Much of the complication of semiconductor fabrication involves the masking steps in terms of alignment (registration of various successive masking steps) and the attendant complexity of fabricating and using the reticles (masks) themselves. Hence, it is a well known goal to minimize the number of masking steps.
In the prior art it is known to fabricate a field effect transistor using as few as 4 masking steps, each with its associated mask. While a 4 mask process is a significant improvement over previous 7 or 9 mask processes, etc. still it would be desirable to further reduce the number of masking steps to further reduce manufacturing costs.